Verilog HDL 18EC56 Module-3 Electronics (EC)VTU Notes 5th Semester pdf,Download Verilog HDL 18EC56 Module-3 Electronics (EC)VTU Notes 5th Semester pdf
| Verilog HDL (Effective from the academic year 2018 -2019) SEMESTER – 5th |
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| Course Code | 18EC56 | CIE Marks | 40 | |
| Number of Contact Hours/Week | 2:2:0 | SEE Marks | 60 | |
| Total Number of Contact Hours | 10 | Exam Hours | 03
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Module-3
Gate-Level Modeling
Gate-Level Modeling: Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays.
Dataflow Modeling: Continuous assignments, delay specification, expressions, operators, operands, operator types. Ll,L2,L3