Verilog HDL 18EC56 Module-4 Electronics (EC)VTU Notes 5th Semester pdf, Download Verilog HDL 18EC56 Module-4 Electronics (EC)VTU Notes 5th Semester pdf
| Verilog HDL (Effective from the academic year 2018 -2019) SEMESTER – 5th |
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| Course Code | 18EC56 | CIE Marks | 40 | |
| Number of Contact Hours/Week | 2:2:0 | SEE Marks | 60 | |
| Total Number of Contact Hours | 10 | Exam Hours | 03
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Module-4
Behavioral Modeling
Behavioral Modeling: Structured procedures, initial and always, blocking and non blocking statements, delay control, generate statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks.
Tasks and Functions: Differences between tasks and functions, declaration, invocation, automatic tasks and functions. Ll,L2,L3