Verilog HDL 18EC56 Module-4 Electronics (EC)VTU Notes 5th Semester pdf, Download Verilog HDL 18EC56 Module-4 Electronics (EC)VTU Notes 5th Semester pdf
(Effective from the academic year 2018 -2019)
SEMESTER – 5th
|Course Code||18EC56||CIE Marks||40|
|Number of Contact Hours/Week||2:2:0||SEE Marks||60|
|Total Number of Contact Hours||10||Exam Hours||03
Behavioral Modeling: Structured procedures, initial and always, blocking and non blocking statements, delay control, generate statement, event control, conditional statements, Multiway branching, loops, sequential and parallel blocks.
Tasks and Functions: Differences between tasks and functions, declaration, invocation, automatic tasks and functions. Ll,L2,L3