Verilog HDL 18EC56 Module-5 Electronics (EC)VTU Notes 5th Semester pdf

Gate-Level Modeling: Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays.

Dataflow Modeling: Continuous assignments, delay specification, expressions, operators, operands, operator types. Ll,L2,L3

Useful Modeling Teclmiques: Procedural continuous assignments, overriding parameters, conditional compilation and execution, useful system tasks.

Logic Synthesis with Verilog: Logic Synthesis, Impact of logic synthesis, Verilog HDL Synthesis, Synthesis design flow,Verification of Gate-Level Netlist. (Chapter 14 till 14.5 of Text). Ll,L2,L3

 

Course Outcomes:

At the end of this course, students will be able to

1. Write Verilog programs in gate, dataflow (RTL), behavioral and switch modeling levels of Abstraction.

2. Design and verify the functionality of digital circuit/system using test benches.

3. Identify the suitable Abstraction level for a particular digital design.

4. Write the programs more effectively using Verilog tasks, functions and directives.

5. Perform timing and delay Simulation and Interpret the various constructs in logic synthesis.

 

Question paper pattern:

• Examination will be conducted for 100 marks with question paper containing 10 full questions, each of 20 marks

• Each full question can have a maximum of 4 sub questions.

• There will be 2 full questions from each module covering all the topics ofthe module.

• Students will have to answer 5 full questions, selecting one full question from each module.

• The total marks will be proportionally reduced to 60 marks as SEE marks is 60.

 

TextBook:

1. Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson Education, Second Edition.